The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 27, 2024

Filed:

Jul. 04, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Chih-Ching Wang, Kinmen, TW;

Wei-Yang Lee, Taipei, TW;

Ming-Chang Wen, Kaohsiung, TW;

Jo-Tzu Hung, Hsinchu, TW;

Wen-Hsing Hsieh, Hsinchu, TW;

Kuan-Lun Cheng, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/10 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 29/1033 (2013.01); H01L 29/4238 (2013.01); H01L 29/66818 (2013.01); H01L 29/785 (2013.01); H01L 2029/7858 (2013.01);
Abstract

Embodiments of the present disclosure provide a method for forming semiconductor device structures. The method includes forming a fin structure having a stack of semiconductor layers comprising first semiconductor layers and second semiconductor layers alternatingly arranged, forming a sacrificial gate structure over a portion of the fin structure, removing the first and second semiconductor layers in a source/drain region of the fin structure that is not covered by the sacrificial gate structure, forming an epitaxial source/drain feature in the source/drain region, removing portions of the sacrificial gate structure to expose the first and second semiconductor layers, removing portions of the second semiconductor layers so that at least one second semiconductor layer has a width less than a width of each of the first semiconductor layers, forming a conformal gate dielectric layer on exposed first and second semiconductor layers, and forming a gate electrode layer on the conformal gate dielectric layer.


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