The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 20, 2024

Filed:

Jul. 15, 2021
Applicant:

Applied Materials, Inc., Santa Clara, CA (US);

Inventors:

Ria Someshwar, Santa Clara, CA (US);

Seshadri Ganguli, Sunnyvale, CA (US);

Lan Yu, Voorheesville, NY (US);

Siddarth Krishnan, Newark, CA (US);

Srinivas Gandikota, Santa Clara, CA (US);

Jacqueline S. Wrench, San Jose, CA (US);

Yixiong Yang, Fremont, CA (US);

Assignee:

Applied Materials, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/45 (2006.01); H01L 21/324 (2006.01); H01L 21/285 (2006.01); H01L 29/40 (2006.01); H01L 29/66 (2006.01); H01L 21/8238 (2006.01);
U.S. Cl.
CPC ...
H01L 29/456 (2013.01); H01L 21/28518 (2013.01); H01L 21/324 (2013.01); H01L 21/823814 (2013.01); H01L 29/401 (2013.01); H01L 29/45 (2013.01); H01L 29/665 (2013.01);
Abstract

Methods for forming a semiconductor structure and semiconductor structures are described. The method comprises patterning a substrate to form a first opening and a second opening, the substrate comprising an n transistor and a p transistor, the first opening over the n transistor and the second opening over the p transistor; pre-cleaning the substrate; depositing a titanium silicide (TiSi) layer on the n transistor and on the p transistor by plasma-enhanced chemical vapor deposition (PECVD); optionally depositing a first barrier layer on the titanium silicide (TiSi) layer and selectively removing the first barrier layer from the p transistor; selectively forming a molybdenum silicide (MoSi) layer on the titanium silicide (TiSi) layer on the n transistor and the p transistor; forming a second barrier layer on the molybdenum silicide (MoSi) layer; and annealing the semiconductor structure. The method may be performed in a processing chamber without breaking vacuum.


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