The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 26, 2023

Filed:

Aug. 09, 2022
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Chen-Hua Yu, Hsinchu, TW;

Yung-Chi Lin, Su-Lin, TW;

Wen-Chih Chiou, Zhunan Township, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/00 (2006.01); H01L 25/18 (2023.01); H01L 23/00 (2006.01); H01L 25/065 (2023.01);
U.S. Cl.
CPC ...
H01L 25/50 (2013.01); H01L 24/33 (2013.01); H01L 24/83 (2013.01); H01L 24/92 (2013.01); H01L 25/0657 (2013.01); H01L 25/18 (2013.01); H01L 2224/08146 (2013.01); H01L 2224/33181 (2013.01); H01L 2224/33505 (2013.01); H01L 2224/33519 (2013.01); H01L 2224/80006 (2013.01); H01L 2224/8083 (2013.01); H01L 2224/83005 (2013.01); H01L 2224/8383 (2013.01); H01L 2224/83896 (2013.01); H01L 2224/92142 (2013.01); H01L 2225/06541 (2013.01); H01L 2225/06589 (2013.01);
Abstract

A device package includes a first die directly bonded to a second die at an interface, wherein the interface comprises a conductor-to-conductor bond. The device package further includes an encapsulant surrounding the first die and the second die and a plurality of through vias extending through the encapsulant. The plurality of through vias are disposed adjacent the first die and the second die. The device package further includes a plurality of thermal vias extending through the encapsulant and a redistribution structure electrically connected to the first die, the second die, and the plurality of through vias. The plurality of thermal vias is disposed on a surface of the second die and adjacent the first die.


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