The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 26, 2023

Filed:

Aug. 27, 2021
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Chuei-Tang Wang, Taichung, TW;

Tzu-Chun Tang, Kaohsiung, TW;

Wei-Ting Chen, Tainan, TW;

Chung-Hao Tsai, Changhua County, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/528 (2006.01); H01L 23/31 (2006.01); H01L 29/66 (2006.01); H01L 23/00 (2006.01); H01L 29/94 (2006.01);
U.S. Cl.
CPC ...
H01L 23/3185 (2013.01); H01L 23/3171 (2013.01); H01L 23/5283 (2013.01); H01L 24/13 (2013.01); H01L 29/66181 (2013.01); H01L 29/945 (2013.01); H01L 2224/13008 (2013.01);
Abstract

A semiconductor package includes an integrated circuit (IC) structure, an insulating encapsulation laterally covering the IC structure, and a redistribution structure disposed on the insulating encapsulation and the IC structure. The redistribution structure is electrically connected to the IC structure. The IC structure includes a first die, a capacitor structure, a dielectric layer laterally covering the first die and the capacitor structure, and a second die disposed on the dielectric layer, the first die, and the capacitor structure. The second die interacts with the capacitor structure, where a bonding interface between the second die and the first die is substantially coplanar with a bonding interface between the second die and the dielectric layer. A manufacturing method of a semiconductor package is also provided.


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