The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 19, 2023

Filed:

Feb. 16, 2022
Applicant:

Applied Materials, Inc., Santa Clara, CA (US);

Inventors:

Shiyu Sun, Santa Clara, CA (US);

Nam Sung Kim, Sunnyvale, CA (US);

Bingxi Sun Wood, Cupertino, CA (US);

Naomi Yoshida, Sunnyvale, CA (US);

Sheng-Chin Kung, Milpitas, CA (US);

Miao Jin, San Jose, CA (US);

Assignee:

APPLIED MATERIALS, INC., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/423 (2006.01); H01L 29/78 (2006.01); H01L 21/02 (2006.01); H01L 29/775 (2006.01); H01L 29/786 (2006.01); H01L 29/06 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/42392 (2013.01); H01L 21/02603 (2013.01); H01L 29/0653 (2013.01); H01L 29/66439 (2013.01); H01L 29/775 (2013.01); H01L 29/7848 (2013.01); H01L 29/78684 (2013.01); H01L 29/78696 (2013.01); H01L 29/0673 (2013.01);
Abstract

Embodiments provide methods for forming nanowire structures, such as, for example, horizontal gate-all-around (hGAA) structures. In one embodiment, a method includes selectively etching material from a stack disposed on a material layer located on a substrate with a plasma to create recesses on each of first and second sides of the stack and depositing a dielectric material on the first and second sides. The stack includes repeating pairs of first and second layers. The method also includes removing the dielectric material from the first and second sides, where the dielectric material remains in the recesses of the first and second sides, and selectively depositing a stressor layer on regions of the first and second sides which are unprotected by the dielectric material to form gaps between the stressor layer and the dielectric material remaining in the recesses of the first and second sides.


Find Patent Forward Citations

Loading…