The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 12, 2023

Filed:

Jul. 27, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Tai-I Yang, Hsinchu, TW;

Cheng-Chi Chuang, New Taipei, TW;

Yung-Chih Wang, Taoyuan, TW;

Tien-Lu Lin, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/528 (2006.01); H01L 21/768 (2006.01); H01L 23/532 (2006.01); H01L 23/522 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5283 (2013.01); H01L 21/7682 (2013.01); H01L 21/76802 (2013.01); H01L 21/76804 (2013.01); H01L 21/76807 (2013.01); H01L 21/76831 (2013.01); H01L 21/76834 (2013.01); H01L 21/76843 (2013.01); H01L 21/76877 (2013.01); H01L 21/76879 (2013.01); H01L 23/5221 (2013.01); H01L 23/53238 (2013.01); H01L 23/53295 (2013.01); H01L 23/5226 (2013.01); H01L 2221/1063 (2013.01); H01L 2924/0002 (2013.01);
Abstract

The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a first interconnect arranged within an inter-level dielectric (ILD) layer. The first interconnect has opposing sidewalls that are both laterally separated from closest neighboring interconnects within the ILD layer by one or more air-gaps along a cross-sectional view. A second interconnect is arranged within the ILD layer. The ILD layer laterally contacts opposing sidewalls of the second interconnect as viewed along the cross-sectional view.


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