The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 28, 2023

Filed:

Aug. 30, 2021
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Chieh-Han Wu, Hsinchu, TW;

Hwei-Jay Chu, Hsinchu, TW;

An-Dih Yu, Hsinchu, TW;

Tzu-Hui Wei, Hsinchu, TW;

Cheng-Hsiung Tsai, Hsinchu, TW;

Chung-Ju Lee, Hsinchu, TW;

Shin-Yi Yang, Hsinchu, TW;

Ming-Han Lee, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/06 (2006.01); H01L 21/768 (2006.01); H01L 23/528 (2006.01); H01L 21/8234 (2006.01);
U.S. Cl.
CPC ...
H01L 29/0649 (2013.01); H01L 21/76829 (2013.01); H01L 21/823481 (2013.01); H01L 23/5283 (2013.01);
Abstract

A method for manufacturing a semiconductor structure includes forming a trench in a dielectric structure; forming a spacer layer on a lateral surface of the dielectric structure exposed by the trench; after forming the spacer layer, forming a first electrically conductive feature in the trench; removing at least portion of the dielectric structure to form a recess; forming an etch stop layer in the recess and over the first electrically conductive feature; and after forming the etch stop layer, depositing a dielectric layer in the recess and over the first electrically conductive feature.


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