The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 28, 2023

Filed:

Dec. 31, 2016
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Zhicheng Ding, Shanghai, CN;

Bin Liu, Shanghai, CN;

Yong She, Songjiang, CN;

Hyoung Il Kim, Folsom, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/065 (2023.01); H01L 21/56 (2006.01); H01L 23/31 (2006.01); H01L 23/498 (2006.01); H01L 23/538 (2006.01); H01L 25/00 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0652 (2013.01); H01L 21/568 (2013.01); H01L 23/3128 (2013.01); H01L 23/49811 (2013.01); H01L 23/5383 (2013.01); H01L 25/0657 (2013.01); H01L 25/50 (2013.01); H01L 2225/0651 (2013.01); H01L 2225/06506 (2013.01); H01L 2225/06562 (2013.01);
Abstract

Electronic device package technology is disclosed. An electronic device package in accordance with the present disclosure can include an electronic component, a redistribution layer, and an interposer electrically coupling the redistribution layer and the electronic component. The interposer can have interconnect interfaces on a top side electrically coupled to the electronic component and interconnect interfaces on a bottom side electrically coupled to the redistribution layer. A density of the interconnect interfaces on the top side can be greater than a density of the interconnect interfaces on the bottom side. Associated systems and methods are also disclosed.


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