The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 28, 2023
Filed:
Apr. 01, 2020
Applicant:
Adeia Semiconductor Technologies Llc, San Jose, CA (US);
Inventors:
Belgacem Haba, San Jose, CA (US);
Stephen Morein, San Jose, CA (US);
Ilyas Mohammed, San Jose, CA (US);
Rajesh Katkar, San Jose, CA (US);
Javier A. Delacruz, San Jose, CA (US);
Assignee:
Invensas LLC, San Jose, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/50 (2006.01); H01L 23/367 (2006.01); H01L 21/48 (2006.01); H01L 23/64 (2006.01); H01L 23/49 (2006.01);
U.S. Cl.
CPC ...
H01L 23/50 (2013.01); H01L 21/4871 (2013.01); H01L 21/4889 (2013.01); H01L 23/367 (2013.01); H01L 23/49 (2013.01); H01L 23/642 (2013.01);
Abstract
Techniques are disclosed herein for creating over and under interconnects. Using techniques described herein, over and under interconnects are created on an IC. Instead of creating signaling interconnects and power/ground interconnects on a same side of a chip assembly, the signaling interconnects can be placed on an opposing side of the chip assembly as compared to the power interconnects.