The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 14, 2023
Filed:
Oct. 04, 2021
Pyxis CF Pte. Ltd., Singapore, SG;
Amlan Sen, Singapore, SG;
Chian Soon Chua, Singapore, SG;
Qing Feng Guan, Singapore, SG;
Wai Hoe Lee, Singapore, SG;
PYXIS CF PTE. LTD., Singapore, SG;
Abstract
Panel level packaging (PLP) with high positional accuracy of dies. The PLP bonds dies accurately to die bonding regions of an alignment panel. High accuracy is achieved by providing die bonding regions with local alignment marks. Accurate die bonding on the alignment carrier results in a reconstructed wafer with accurate positioning of dies. The dies of the reconstructed wafer can be scanned by a die location check (DLC) scan based on sub-blocks of dies, enabling high DLC throughput. The DLC scan generates a DLC file with coordinate points of sub-blocks of the reconstructed wafer. Also, a laser direct imaging (LDI) file can be generated using sub-block circuit files aligned to the DLC file. The use of sub-block circuit files facilitates high throughput in generating the LDI file with high accuracy due to the reconstructed wafer being formed using the alignment carrier with local alignment marks.