The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 31, 2023

Filed:

Mar. 18, 2022
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Yu-Chu Lin, Tainan, TW;

Chi-Chung Jen, Kaohsiung, TW;

Chia-Ming Pan, Tainan, TW;

Su-Yu Yeh, Tainan, TW;

Keng-Ying Liao, Tainan, TW;

Chih-Wei Sung, Kaohsiung, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 21/28 (2006.01); H01L 29/788 (2006.01); H10B 41/30 (2023.01);
U.S. Cl.
CPC ...
H01L 29/42328 (2013.01); H01L 29/40114 (2019.08); H01L 29/66825 (2013.01); H01L 29/7881 (2013.01); H10B 41/30 (2023.02);
Abstract

A method includes depositing a gate dielectric film over a substrate. A floating gate layer and a control gate layer are deposited over the gate dielectric film. The control gate layer is patterned to form a control gate over the floating gate layer. A top portion of the floating gate layer is patterned. A spacer structure is formed on a sidewall of the control gate and over a remaining portion of the floating gate layer. The remaining portion of the floating gate layer is patterned to form a bottom portion of a floating gate. A ratio of the bottom width of the bottom portion to the middle width of the bottom portion is in a range between about 103% and about 108%. The gate dielectric film is patterned form a gate dielectric layer.


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