The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 24, 2023

Filed:

Nov. 17, 2021
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Tzu-Yu Chen, Kaohsiung, TW;

Kuo-Chi Tu, Hsin-Chu, TW;

Sheng-Hung Shih, Hsinchu, TW;

Wen-Ting Chu, Kaohsiung, TW;

Chih-Hsiang Chang, Taichung, TW;

Fu-Chen Chang, New Taipei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 53/00 (2023.01); G11C 11/22 (2006.01); H10B 53/10 (2023.01); H10B 53/30 (2023.01); H01L 49/02 (2006.01);
U.S. Cl.
CPC ...
H10B 53/00 (2023.02); G11C 11/221 (2013.01); H01L 28/55 (2013.01); H01L 28/60 (2013.01); H10B 53/10 (2023.02); H10B 53/30 (2023.02);
Abstract

The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a bottom electrode disposed over a substrate. A data storage structure is disposed on the bottom electrode and is configured to store a data state. A top electrode is disposed on the data storage structure. The top electrode has interior surfaces defining a recess within an upper surface of the top electrode. A masking layer contacts a bottom of the recess and extends to over the upper surface of the top electrode. An interconnect extends through the masking layer and to the top electrode. The interconnect is directly over the upper surface of the top electrode.


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