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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11792989 B1

PDFFull Text
Date of Patent:
Oct. 17, 2023

Filed:

Oct. 25, 2021

Word line structure of three-dimensional memory device

Applicant:

Yangtze Memory Technologies Co., Ltd., Hubei, CN;

Inventors:

Qiang Xu, Hubei, CN;

Fandong Liu, Hubei, CN;

Zongliang Huo, Hubei, CN;

Zhiliang Xia, Hubei, CN;

Yaohua Yang, Hubei, CN;

Peizhen Hong, Hubei, CN;

Wenyu Hua, Hubei, CN;

Jia He, Hubei, CN;

Assignee:

Yangtze Memory Technologies Co., Ltd., Hubei, CN;

Attorney:

Sterne, Kessler, Goldstein & Fox P.L.L.C.

Primary Examiner:

Julia Slutsker

Int. Cl.
CPC ...
H10B 43/27 (2023.01); H10B 43/10 (2023.01); H10B 43/30 (2023.01); H10B 43/35 (2023.01); H10B 43/40 (2023.01); H10B 43/50 (2023.01); H01L 21/02 (2006.01); H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 29/08 (2006.01); H01L 29/10 (2006.01); H01L 21/285 (2006.01); H01L 21/3105 (2006.01); H01L 21/311 (2006.01); H01L 23/532 (2006.01);
U.S. Cl.
CPC ...
H10B 43/27 (2023.02); H01L 21/02164 (2013.01); H01L 21/76802 (2013.01); H01L 21/76877 (2013.01); H01L 21/76895 (2013.01); H01L 23/528 (2013.01); H01L 23/5226 (2013.01); H01L 29/0847 (2013.01); H01L 29/1037 (2013.01); H10B 43/10 (2023.02); H10B 43/30 (2023.02); H10B 43/35 (2023.02); H10B 43/40 (2023.02); H10B 43/50 (2023.02); H01L 21/0262 (2013.01); H01L 21/02271 (2013.01); H01L 21/28568 (2013.01); H01L 21/31053 (2013.01); H01L 21/31111 (2013.01); H01L 21/31144 (2013.01); H01L 23/53214 (2013.01); H01L 23/53228 (2013.01); H01L 23/53257 (2013.01);
Abstract

Methods and structures of a three-dimensional memory device are disclosed. In an example, the memory device comprises a substrate, a stack structure on the substrate, and at least one gate line slit extending along a first direction substantially parallel to a top surface of the substrate, and dividing the stack structure into at least two portions. The stack structure includes at least one connection portion that divides the at least one gate line slit, and conductively connects the at least two portions.

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