The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 17, 2023
Filed:
May. 10, 2021
International Business Machines Corporation, Armonk, NY (US);
Kamal K Sikka, Poughkeepsie, NY (US);
Maryse Cournoyer, Granby, CA;
Pascale Gagnon, Brigham, CA;
Charles C. Bureau, Bromont, CA;
Catherine Dufort, Bromont, CA;
Dale Curtis McHerron, Staatsburg, NY (US);
Vijayeshwar Das Khanna, Millwood, NY (US);
Marc A. Bergendahl, Rensselaer, NY (US);
Dishit Paresh Parekh, Guilderland, NY (US);
Ravi K. Bonam, Albany, NY (US);
Hiroyuki Mori, Yasu, JP;
Yang Liu, Yorktown Heights, NY (US);
Paul S. Andry, Yorktown Heights, NY (US);
Isabel De Sousa, Chambly, CA;
International Business Machines Corporation, Armonk, NY (US);
Abstract
A direct bonded heterogeneous integration (DBHi) device includes a substrate including a trench formed in a top surface of the substrate. The DBHi device further includes a first chip coupled to the substrate on a first side of the trench by a plurality of first interconnects. The DBHi device further includes a second chip coupled to the substrate on a second side of the trench by a plurality of second interconnects. The second side of the trench is arranged opposite the first side of the trench. The DBHi device further includes a bridge coupled to the first chip and to the second chip by a plurality of third interconnects such that the bridge is suspended in the trench. The DBHi device further includes a non-conductive paste material surrounding the plurality of third interconnects to further couple the bridge to the first chip and to the second chip.