The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 17, 2023

Filed:

Mar. 14, 2022
Applicant:

Yangtze Memory Technologies Co., Ltd., Hubei, CN;

Inventors:

Jifeng Zhu, Hubei, CN;

Jun Chen, Hubei, CN;

Si Ping Hu, Hubei, CN;

Zhenyu Lu, Hubei, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/528 (2006.01); H01L 21/02 (2006.01); H01L 21/3213 (2006.01); H01L 21/683 (2006.01); H01L 21/768 (2006.01); H01L 23/522 (2006.01); H10B 41/27 (2023.01); H10B 43/27 (2023.01); H01L 21/3105 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5283 (2013.01); H01L 21/0262 (2013.01); H01L 21/02271 (2013.01); H01L 21/02488 (2013.01); H01L 21/02532 (2013.01); H01L 21/3213 (2013.01); H01L 21/6835 (2013.01); H01L 21/76892 (2013.01); H01L 21/76895 (2013.01); H01L 21/76898 (2013.01); H01L 23/5226 (2013.01); H10B 41/27 (2023.02); H10B 43/27 (2023.02); H01L 21/0217 (2013.01); H01L 21/0223 (2013.01); H01L 21/02164 (2013.01); H01L 21/02211 (2013.01); H01L 21/02255 (2013.01); H01L 21/02595 (2013.01); H01L 21/02598 (2013.01); H01L 21/31053 (2013.01); H01L 2221/68363 (2013.01); H01L 2221/68381 (2013.01);
Abstract

Embodiments of methods and structures for forming a 3D integrated wiring structure are disclosed. The method can include forming an insulating layer on a front side of a first substrate; forming a semiconductor layer on a front side of the insulating layer; patterning the semiconductor layer to expose at least a portion of a surface of the insulating layer; forming a plurality of semiconductor structures over the front side of the first substrate, wherein the semiconductor structures include a plurality of conductive contacts and a first conductive layer; joining a second substrate with the semiconductor structures; performing a thinning process on a backside of the first substrate to expose the insulating layer and one end of the plurality of conductive contacts; and forming a conductive wiring layer on the exposed insulating layer.


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