The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 17, 2023
Filed:
Aug. 10, 2022
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Fong-Yuan Chang, Hsinchu, TW;
Chin-Chou Liu, Hsinchu, TW;
Hui-Zhong Zhuang, Hsinchu, TW;
Meng-Kai Hsu, Hsinchu, TW;
Pin-Dai Sue, Hsinchu, TW;
Po-Hsiang Huang, Hsinchu, TW;
Yi-Kan Cheng, Hsinchu, TW;
Chi-Yu Lu, Hsinchu, TW;
Jung-Chou Tsai, Hsinchu, TW;
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu, TW;
Abstract
A system for generating a layout diagram of a wire routing arrangement in a multi-patterning context having multiple masks (the layout diagram being stored on a non-transitory computer-readable medium), at least one processor, at least one memory and computer program code (for one or more programs) of the system being configured to cause the system to execute generating the layout diagram including: placing, relative to a given one of the masks, a given cut pattern at a first candidate location over a corresponding portion of a given conductive pattern in a metallization layer; determining whether the first candidate location results in at least one of a non-circular group or a cyclic group which violates a design rule; and temporarily preventing placement of the given cut pattern in the metallization layer at the first candidate location until a correction is made which avoids violating the design rule.