The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 10, 2023

Filed:

May. 19, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Fu-Ting Sung, Yangmei, TW;

Chung-Chiang Min, Zhubei, TW;

Yuan-Tai Tseng, Zhubei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/02 (2006.01); H10B 63/00 (2023.01); G11C 5/06 (2006.01); G11C 13/00 (2006.01); H10N 70/20 (2023.01); H10N 70/00 (2023.01);
U.S. Cl.
CPC ...
H10B 63/00 (2023.02); G11C 5/06 (2013.01); G11C 13/0011 (2013.01); H10N 70/245 (2023.02); H10N 70/823 (2023.02);
Abstract

Some embodiments relate to a method for forming a memory device. The method includes forming a lower dielectric layer over a conductive wire. A stack of memory layers is formed within the lower dielectric layer and over the conductive wire. The stack of memory layers comprises a top electrode, a bottom electrode, and a data storage layer between the top electrode and the bottom electrode. A removal process is performed on the stack of memory layers to define a programmable metallization cell that comprises the top electrode, the bottom electrode, and the data storage layer. The programmable metallization cell comprises a central region and a peripheral region that extends upwardly from the central region. A top surface of the programmable metallization cell and a top surface of the lower dielectric layer are coplanar.


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