The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 19, 2023

Filed:

Sep. 02, 2021
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Ravi Pillarisetty, Portland, OR (US);

Brian S. Doyle, Portland, OR (US);

Abhishek A. Sharma, Hillsboro, OR (US);

Prashant Majhi, San Jose, CA (US);

Willy Rachmady, Beaverton, OR (US);

Jack T. Kavalieros, Portland, OR (US);

Gilbert Dewey, Beaverton, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/51 (2006.01); H01L 21/28 (2006.01); H01L 29/40 (2006.01); H01L 29/49 (2006.01); H10B 61/00 (2023.01); H10B 63/00 (2023.01);
U.S. Cl.
CPC ...
H01L 29/517 (2013.01); H01L 21/28176 (2013.01); H01L 29/401 (2013.01); H01L 29/4966 (2013.01); H10B 61/22 (2023.02); H10B 63/30 (2023.02);
Abstract

A transistor, including an antiferroelectric (AFE) gate dielectric layer is described. The AFE gate dielectric layer may be crystalline and include oxygen and a dopant. The transistor further includes a gate electrode on the AFE gate dielectric layer, a source structure and a drain structure on the substrate, where the gate electrode is between the source structure and the drain structure. The transistor further includes a source contact coupled with the source structure and a drain contact coupled with the drain structure.


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