The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 12, 2023

Filed:

May. 27, 2021
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Te-An Yu, Taipei, TW;

Hung-Ju Chou, Taipei, TW;

Jet-Rung Chang, Hsinchu County, TW;

Yen-Po Lin, Taipei, TW;

Jiun-Ming Kuo, Taipei, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/22 (2006.01); H01L 29/66 (2006.01); H01L 21/223 (2006.01); H01L 21/02 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/786 (2006.01);
U.S. Cl.
CPC ...
H01L 29/6653 (2013.01); H01L 21/223 (2013.01); H01L 29/66545 (2013.01); H01L 29/66553 (2013.01); H01L 29/66742 (2013.01); H01L 21/0245 (2013.01); H01L 21/02507 (2013.01); H01L 21/02513 (2013.01); H01L 21/02532 (2013.01); H01L 21/02576 (2013.01); H01L 29/0665 (2013.01); H01L 29/42392 (2013.01); H01L 29/6656 (2013.01); H01L 29/78696 (2013.01);
Abstract

A method for forming a semiconductor device structure is provided. The method includes forming an n-type doped region in a semiconductor substrate and forming a semiconductor stack over the semiconductor substrate. The semiconductor stack has multiple sacrificial layers and multiple semiconductor layers laid out alternately. The method also includes introducing n-type dopants from the n-type doped region into the semiconductor stack during the forming of the semiconductor stack. The method further includes patterning the semiconductor stack to form a fin structure and forming a dummy gate stack to wrap around a portion of the fin structure. In addition, the method includes removing the dummy gate stack and the sacrificial layers to release multiple semiconductor nanostructures made up of remaining portions of the semiconductor layers. The method includes forming a metal gate stack to wrap around the semiconductor nanostructures.


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