The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 05, 2023
Filed:
Dec. 28, 2017
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/10 (2006.01); H01L 23/00 (2006.01); H01L 25/065 (2023.01); H01L 25/00 (2006.01);
U.S. Cl.
CPC ...
H01L 25/105 (2013.01); H01L 24/32 (2013.01); H01L 24/49 (2013.01); H01L 24/73 (2013.01); H01L 24/85 (2013.01); H01L 25/0657 (2013.01); H01L 25/50 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/4901 (2013.01); H01L 2224/4905 (2013.01); H01L 2224/49107 (2013.01); H01L 2224/73265 (2013.01); H01L 2225/0651 (2013.01); H01L 2225/06562 (2013.01); H01L 2225/1017 (2013.01); H01L 2225/1052 (2013.01);
Abstract
A vertical-wire package-in-package includes at least two memory-die stacks that form respective memory modules that are stacked vertically on a bond-wire board. Each memory die in the memory-die stack includes a vertical bond wire that emerges from a matrix for connection. The matrix encloses the memory-die stack, the spacer, and a redistribution layer. At least two memory modules are assembled in a vertical-wire package-in-package.