The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 05, 2023
Filed:
Dec. 15, 2021
Applicant:
Applied Materials, Inc., Santa Clara, CA (US);
Inventors:
Chang Seok Kang, Santa Clara, CA (US);
Tomohiko Kitajima, San Jose, CA (US);
Gill Yong Lee, San Jose, CA (US);
Sanjay Natarajan, Portland, OR (US);
Sung-Kwan Kang, San Jose, CA (US);
Lequn Liu, San Jose, CA (US);
Assignee:
Applied Materials, Inc., Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 5/06 (2006.01); H10B 12/00 (2023.01);
U.S. Cl.
CPC ...
G11C 5/063 (2013.01); H10B 12/02 (2023.02); H10B 12/03 (2023.02); H10B 12/0335 (2023.02); H10B 12/05 (2023.02); H10B 12/30 (2023.02); H10B 12/318 (2023.02); H10B 12/482 (2023.02); H10B 12/488 (2023.02);
Abstract
Memory devices are described. The memory devices include a plurality of bit lines extending through a stack of alternating memory layers and dielectric layers. Each of the memory layers comprises a single crystalline-like silicon layer and includes a first word line, a second word line, a first capacitor, and a second capacitor. Methods of forming stacked memory devices are also described.