The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 22, 2023

Filed:

Jul. 26, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Chen-Han Wang, Zhubei, TW;

Pei-Hsun Wang, Kaohsiung, TW;

Chun-Hsiung Lin, Zhubei, TW;

Chih-Hao Wang, Hsinchu County, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 21/02 (2006.01); H01L 29/08 (2006.01); H01L 29/06 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/785 (2013.01); H01L 21/02532 (2013.01); H01L 21/02554 (2013.01); H01L 21/02603 (2013.01); H01L 29/0669 (2013.01); H01L 29/0847 (2013.01); H01L 29/66795 (2013.01);
Abstract

Methods for manufacturing a semiconductor structure are provided. The semiconductor structure includes a substrate a substrate and channel layers vertically stacked over the substrate. The semiconductor structure also includes a dielectric fin structure formed adjacent to the channel layers and a gate structure abutting the channel layers and the dielectric fin structure. The semiconductor structure also includes a source/drain structure attached to the channel layers and a contact formed over the source/drain structure. The semiconductor structure also includes a Si layer covering a portion of a top surface of the source/drain structure. In addition, the Si layer is sandwiched between the dielectric fin structure and the contact.


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