The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 22, 2023

Filed:

Sep. 30, 2020
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Chih-Yu Hsu, Hsinchu County, TW;

Jian-Hao Chen, Hsinchu, TW;

Chia-Wei Chen, Hsinchu, TW;

Shan-Mei Liao, Hsinchu, TW;

Hui-Chi Chen, Hsinchu County, TW;

Cheng Hong Yang, Hsinchu, TW;

Shih-Hao Lin, Hsinchu, TW;

Kuo-Feng Yu, Hsinchu County, TW;

Feng-Cheng Yang, Hsinchu County, TW;

Yen-Ming Chen, Hsin-Chu County, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/8234 (2006.01); H01L 21/3213 (2006.01); H01L 21/8238 (2006.01); H01L 29/66 (2006.01); H01L 27/092 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823857 (2013.01); H01L 21/823821 (2013.01); H01L 27/0924 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01);
Abstract

Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a first semiconductor stack and a second semiconductor stack over a substrate, wherein each of the first and second semiconductor stacks includes semiconductor layers stacked up and separated from each other; a dummy spacer between the first and second semiconductor stacks, wherein the dummy spacer contacts a first sidewall of each semiconductor layer of the first and second semiconductor stacks; and a gate structure wrapping a second sidewall, a top surface, and a bottom surface of each semiconductor layer of the first and second semiconductor stacks.


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