The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 08, 2023

Filed:

Jun. 29, 2018
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Uygar Avci, Portland, OR (US);

Ian Young, Portland, OR (US);

Daniel Morris, Hillsboro, OR (US);

Seiyon Kim, Portland, OR (US);

Yih Wang, Portland, OR (US);

Ruth Brain, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/522 (2006.01); H01L 21/768 (2006.01); H10B 12/00 (2023.01); H01L 49/02 (2006.01);
U.S. Cl.
CPC ...
H10B 12/315 (2023.02); H01L 21/76808 (2013.01); H01L 21/76843 (2013.01); H01L 23/5226 (2013.01); H01L 28/91 (2013.01); H10B 12/033 (2023.02); H10B 12/50 (2023.02);
Abstract

Embodiments include an embedded dynamic random access memory (DRAM) device, a method of forming an embedded DRAM device, and a memory device. An embedded DRAM device includes a dielectric having a logic area and a memory area, and a trace and a via disposed in the logic area of dielectric. The embedded DRAM device further includes ferroelectric capacitors disposed in the memory area of dielectric, where each ferroelectric capacitor includes a first electrode, a ferroelectric layer, and a second electrode, and where the ferroelectric layer surrounds the first electrode of each ferroelectric capacitor and extends along a top surface of the dielectric in the memory area. The embedded DRAM device includes an etch stop layer above the dielectric. The second etch stop in the logic area may have a z-height that is approximately equal to a z-height of a top surface of the second etch stop in the memory area.


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