The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 08, 2023

Filed:

Jun. 29, 2022
Applicants:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Tsmc Nanjing Company Limited, Nanjing, CN;

Tsmc China Company Limited, Shanghai, CN;

Inventors:

He-Zhou Wan, Shanghai, CN;

Xiu-Li Yang, Shanghai, CN;

Pei-Le Li, Nanjing, CN;

Ching-Wei Wu, Nantou County, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/10 (2006.01); G11C 7/12 (2006.01); G11C 5/14 (2006.01); G11C 8/10 (2006.01);
U.S. Cl.
CPC ...
G11C 7/109 (2013.01); G11C 5/147 (2013.01); G11C 5/148 (2013.01); G11C 7/1057 (2013.01); G11C 7/1063 (2013.01); G11C 7/1069 (2013.01); G11C 7/1084 (2013.01); G11C 7/1096 (2013.01); G11C 7/12 (2013.01); G11C 8/10 (2013.01);
Abstract

A memory device includes a local input/output circuit and a main input/output circuit. The local input/output circuit is configured to generate a first local write signal based on a first global write signal and a second global write signal, and configured to transmit the first local write signal to a plurality of first bit lines. The main input/output circuit include a first latch and logic elements. The first latch is configured to generate a first bit write mask signal based on a clock signal. The logic elements are configured to generate the first global write signal and the second global write signal based on the clock signal and the first bit write mask signal.


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