The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 18, 2023

Filed:

Oct. 08, 2019
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Chandra Mohan Jha, Tempe, AZ (US);

Prasad Ramanathan, Chandler, AZ (US);

Xavier F. Brun, Chandler, AZ (US);

Jimmin Yao, Chandler, AZ (US);

Mark Allen, Gilbert, AZ (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 23/52 (2006.01); H01L 23/00 (2006.01); H01L 23/532 (2006.01); H01L 23/373 (2006.01); H01L 23/31 (2006.01);
U.S. Cl.
CPC ...
H01L 24/14 (2013.01); H01L 23/3114 (2013.01); H01L 23/3128 (2013.01); H01L 23/3735 (2013.01); H01L 23/53209 (2013.01);
Abstract

Embodiments include semiconductor packages and methods to form the semiconductor packages. A semiconductor package includes a plurality of first dies on a substrate, an interface layer over the first dies, a backside metallization (BSM) layer directly on the interface layer, where the BSM layer includes first, second, and third conductive layer, and a heat spreader over the BSM layer. The first conductive layer includes a titanium material. The second conductive layer includes a nickel-vanadium material. The third conductive layer includes a gold material, a silver material, or a copper material. The copper material may include copper bumps. The semiconductor package may include a plurality of second dies on a package substrate. The substrate may be on the package substrate. The second dies may have top surfaces substantially coplanar to top surface of the first dies. The BSM and interface layers may be respectively over the first and second dies.


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