The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 11, 2023
Filed:
Apr. 25, 2022
Ldmos transistors including vertical gates with multiple dielectric sections, and associated methods
Maxim Integrated Products, Inc., San Jose, CA (US);
Tom K. Castro, Santa Clara, CA (US);
Rajwinder Singh, Pleasanton, CA (US);
Badredin Fatemizadeh, Palo Alto, CA (US);
Adam Brand, Palo Alto, CA (US);
John Xia, Fremont, CA (US);
Chi-Nung Ni, Foster City, CA (US);
Marco A. Zuniga, Berkeley, CA (US);
Maxim Integrated Products, Inc., San Jose, CA (US);
Abstract
A lateral double-diffused metal-oxide-semiconductor transistor includes a silicon semiconductor structure and a vertical gate. The vertical gate include a (a) gate conductor extending from a first outer surface of the silicon semiconductor structure into the silicon semiconductor structure and (b) a gate dielectric layer including a least three dielectric sections. Each of the at least three dielectric sections separates the gate conductor from the silicon semiconductor structure by a respective separation distance, where each of the respective separation distances is different from each other of the respective separation distances.