The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 27, 2023

Filed:

Mar. 26, 2021
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Andrew M. Greene, Slingerlands, NY (US);

Julien Frougier, Albany, NY (US);

Jingyun Zhang, Albany, NY (US);

Sung Dae Suk, Watervliet, NY (US);

Veeraraghavan S. Basker, Schenectady, NY (US);

Ruilong Xie, Niskayuna, NY (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/092 (2006.01); H01L 21/8238 (2006.01); H01L 29/78 (2006.01); H01L 29/06 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0924 (2013.01); H01L 21/823821 (2013.01); H01L 29/0649 (2013.01); H01L 29/785 (2013.01); H01L 2029/7858 (2013.01);
Abstract

A semiconductor device is provided. The semiconductor device includes a semiconductor substrate; a transistor stack structure formed on the semiconductor substrate, the transistor stack structure including a first FET and a second FET, where the first FET is a different polarity than the second FET; a first source-drain epitaxial layer of the first FET formed directly on the substrate adjacent to the first FET; and a second source-drain epitaxial layer of the second FET formed on the substrate adjacent to the second FET, wherein a bottom dielectric isolation layer is formed between the substrate and the second epitaxial layer.


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