The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 20, 2023
Filed:
Nov. 26, 2018
Applicant:
Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;
Inventors:
Po-Hao Tsai, Zhongli, TW;
Techi Wong, Zhubei, TW;
Meng-Wei Chou, Zhubei, TW;
Meng-Liang Lin, Hsinchu, TW;
Po-Yao Chuang, Hsin-Chu, TW;
Shin-Puu Jeng, Hsinchu, TW;
Assignee:
TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/31 (2006.01); H01L 23/498 (2006.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 23/538 (2006.01);
U.S. Cl.
CPC ...
H01L 23/3114 (2013.01); H01L 21/4857 (2013.01); H01L 21/563 (2013.01); H01L 23/3128 (2013.01); H01L 23/49822 (2013.01); H01L 23/5389 (2013.01);
Abstract
A method for forming a chip package structure is provided. The method includes disposing a chip over a redistribution structure. The method includes forming a molding layer over the redistribution structure and adjacent to the chip. The method includes partially removing the molding layer to form a trench in the molding layer, and the trench is spaced apart from the chip.