The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 20, 2023

Filed:

May. 27, 2022
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;

Inventors:

Chao-Hsun Wang, Taoyuan County, TW;

Hsien-Cheng Wang, Hsinchu, TW;

Mei-Yun Wang, Hsin-Chu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/485 (2006.01); H01L 21/768 (2006.01); H01L 21/311 (2006.01); H01L 21/8234 (2006.01); H01L 29/08 (2006.01); H01L 29/40 (2006.01); H01L 29/43 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76816 (2013.01); H01L 21/31111 (2013.01); H01L 21/31116 (2013.01); H01L 21/76831 (2013.01); H01L 21/823475 (2013.01); H01L 23/485 (2013.01); H01L 29/0847 (2013.01); H01L 29/401 (2013.01); H01L 29/435 (2013.01); H01L 21/76895 (2013.01);
Abstract

A semiconductor device includes a gate structure disposed over a substrate, and a first dielectric layer disposed over the substrate, including and over the gate structure. A first metal feature is disposed in the first dielectric layer, including an upper portion having a first width and a lower portion having a second width that is different than the first width. A dielectric spacer is disposed along the lower portion of the first metal feature, wherein the upper portion of the first metal feature is disposed over the dielectric spacer. A second dielectric layer is disposed over the first dielectric layer, including over the first metal feature and a second metal feature extends through the second dielectric layer to physically contact with the first metal feature. A third metal feature extends through the second dielectric layer and the first dielectric layer to physically contact the gate structure.


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