The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 06, 2023
Filed:
Jun. 20, 2019
Intel Corporation, Santa Clara, CA (US);
Aaron D. Lilak, Beaverton, OR (US);
Patrick R. Morrow, Portland, OR (US);
Hui Jae Yoo, Hillsboro, OR (US);
Sean T. Ma, Portland, OR (US);
Scott B. Clendenning, Portland, OR (US);
Abhishek A. Sharma, Hillsboro, OR (US);
Ehren Mannebach, Tigard, OR (US);
Urusa Alaan, Hillsboro, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
A memory structure includes conductive lines extending horizontally in a spaced apart fashion within a vertical stack above a base or substrate. The vertical stack includes a plurality of conductive lines, the first and second conductive lines being part of the plurality. A gate structure extends vertically through the first and second conductive lines. The gate structure includes a body of semiconductor material and a dielectric, where the dielectric is between the body and the conductive lines. An isolation material is on at least one side of the vertical stack and in contact with the conductive lines. The vertical stack defines a void located vertically between at the first and second conductive lines in the vertical stack and laterally between the gate structure and the isolation material. The void may extend along a substantial length (e.g., 20 nm or more) of the first and second conductive lines.