The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 30, 2023

Filed:

May. 10, 2021
Applicant:

Nxp Usa, Inc., Austin, TX (US);

Inventors:

Hernan Rueda, Chandler, AZ (US);

Rodney Arlan Barksdale, Buda, TX (US);

Stephen C Chew, Dripping Springs, TX (US);

Martin Garcia, Buda, TX (US);

Wayne Geoffrey Risner, Austin, TX (US);

Assignee:

NXP USA, Inc., Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 29/08 (2006.01); H01L 29/40 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66689 (2013.01); H01L 29/086 (2013.01); H01L 29/0878 (2013.01); H01L 29/401 (2013.01); H01L 29/402 (2013.01); H01L 29/6656 (2013.01); H01L 29/66553 (2013.01); H01L 29/7816 (2013.01);
Abstract

A method for manufacturing a Laterally Diffused Metal Oxide Semiconductor (LDMOS) transistor with implant alignment spacers includes etching a gate stack comprising a first nitride layer. The first nitride layer is on a silicon layer. The gate stack is separated from a substrate by a first oxide layer. The gate stack is oxidized to form a polysilicon layer from the silicon layer, and to form a second oxide layer on a sidewall of the polysilicon layer. A drain region of the LDMOS transistor is implanted with a first implant aligned to a first edge formed by the second oxide layer. A second nitride layer is formed conformingly covering the second oxide layer. A nitride etch-stop layer is formed conformingly covering the second nitride layer.


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