The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 30, 2023

Filed:

Jan. 08, 2021
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;

Inventors:

Aurelien Gauthier Brun, Hsin-Chu, TW;

Chun Lin Tsai, Hsin-Chu, TW;

Jiun-Lei Jerry Yu, Zhudong Township, TW;

Po-Chih Chen, Hsinchu, TW;

Yun-Hsiang Wang, Hsin-Chu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/417 (2006.01); H01L 29/40 (2006.01); H01L 29/423 (2006.01); H01L 29/778 (2006.01);
U.S. Cl.
CPC ...
H01L 29/41758 (2013.01); H01L 29/401 (2013.01); H01L 29/402 (2013.01); H01L 29/4238 (2013.01); H01L 29/7786 (2013.01);
Abstract

The present disclosure relates to a transistor device. The transistor device includes a plurality of first source/drain contacts disposed over a substrate. A plurality of gate structures are disposed over the substrate between the plurality of first source/drain contacts. The plurality of gate structures wrap around the plurality of first source/drain contacts in a plurality of closed loops. A second source/drain contact is disposed over the substrate between the plurality of gate structures. The second source/drain contact continuously wraps around the plurality of gate structures as a continuous structure.


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