The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 23, 2023

Filed:

Jun. 10, 2021
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Chih-Lin Chen, Hsinchu, TW;

Hui-Yu Lee, Hsinchu, TW;

Fong-Yuan Chang, Hsinchu, TW;

Po-Hsiang Huang, Hsinchu, TW;

Chin-Chou Liu, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/065 (2006.01); H01L 21/768 (2006.01); H01L 23/48 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 23/538 (2006.01); H01L 49/02 (2006.01); H01L 23/00 (2006.01); H01L 25/00 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0657 (2013.01); H01L 21/76898 (2013.01); H01L 23/481 (2013.01); H01L 23/528 (2013.01); H01L 23/5227 (2013.01); H01L 23/5389 (2013.01); H01L 24/32 (2013.01); H01L 24/83 (2013.01); H01L 25/50 (2013.01); H01L 28/10 (2013.01); H01L 2224/08145 (2013.01); H01L 2224/83896 (2013.01); H01L 2225/06524 (2013.01); H01L 2225/06531 (2013.01); H01L 2225/06541 (2013.01); H01L 2924/1206 (2013.01); H01L 2924/19042 (2013.01);
Abstract

An integrated circuit includes a first semiconductor wafer, a second semiconductor wafer, a first interconnect structure, an inductor, and a through substrate via. The first semiconductor wafer has a first device in a first side of the first semiconductor wafer. The second semiconductor wafer is over the first semiconductor wafer. The first interconnect structure is on a second side of the first semiconductor wafer opposite from the first side of the first semiconductor wafer. The inductor is below the first semiconductor wafer, and at least a portion of the inductor is within the first interconnect structure. The through substrate via extends through the first semiconductor wafer. The inductor is coupled to at least the first device by at least the through substrate via.


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