The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 09, 2023
Filed:
Jul. 08, 2021
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Kong-Beng Thei, Pao-Shan Village, TW;
Dun-Nian Yaung, Taipei, TW;
Fu-Jier Fan, Hsinchu, TW;
Hsing-Chih Lin, Tainan, TW;
Hsiao-Chin Tuan, Taowan, TW;
Jen-Cheng Liu, Hsin-Chu, TW;
Alexander Kalnitsky, San Francisco, CA (US);
Yi-Sheng Chen, Hsinchu, TW;
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Abstract
A three-dimensional (3D) integrated circuit (IC) is provided. In some embodiments, a second IC die is bonded to a first IC die. A seal-ring structure is arranged in a peripheral region of the 3D IC in the first IC die and the second IC die. The seal-ring structure extends from a first semiconductor substrate of the first IC die to a second semiconductor substrate of the second IC die. A plurality of through silicon via (TSV) coupling structures is arranged at the peripheral region of the 3D IC along an inner perimeter of the seal-ring structure closer to the 3D IC than the seal-ring structure. The plurality of TSV coupling structures respectively comprises a TSV disposed in the second semiconductor substrate and electrically coupling to the 3D IC through a stack of TSV wiring layers and inter-wire vias.