The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 09, 2023

Filed:

Sep. 29, 2021
Applicant:

Mediatek Inc., Hsinchu, TW;

Inventors:

Chia-Cheng Chang, Hsinchu, TW;

Tzu-Hung Lin, Hsinchu, TW;

I-Hsuan Peng, Hsinchu, TW;

Yi-Jou Lin, Hsinchu, TW;

Assignee:

MEDIATEK INC., Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/065 (2006.01); H01L 23/538 (2006.01); H01L 23/31 (2006.01); H01L 23/498 (2006.01); H01L 23/00 (2006.01); H01L 23/367 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0655 (2013.01); H01L 23/3128 (2013.01); H01L 23/49816 (2013.01); H01L 23/5386 (2013.01); H01L 23/3675 (2013.01); H01L 24/16 (2013.01); H01L 2224/16113 (2013.01); H01L 2224/16227 (2013.01); H01L 2924/3511 (2013.01);
Abstract

A semiconductor package structure includes a substrate having a substrate having a first surface and second surface opposite thereto, wherein the substrate comprises a wiring structure. The structure also has a first semiconductor die disposed on the first surface of the substrate and electrically coupled to the wiring structure, and a second semiconductor die disposed on the first surface and electrically coupled to the wiring structure, wherein the first semiconductor die and the second semiconductor die are arranged in a side-by-side manner. A molding material surrounds the first semiconductor die and the second semiconductor die, wherein the first semiconductor die is separated from the second semiconductor die by the molding material. Finally, an annular frame mounted on the first surface of the substrate, wherein the annular frame surrounds the first semiconductor die and the second semiconductor die.


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