The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 02, 2023

Filed:

Dec. 19, 2019
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Jordan Hsu, New Taipei, TW;

Yu-Kuan Lin, Taipei, TW;

Shau-Wei Lu, Taoyuan, TW;

Chang-Ta Yang, Hsinchu, TW;

Ping-Wei Wang, Hsinchu, TW;

Kuo-Hung Lo, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/11 (2006.01); H01L 21/8238 (2006.01); H01L 27/088 (2006.01); H01L 21/8234 (2006.01); H01L 27/092 (2006.01); H01L 29/66 (2006.01); H01L 29/49 (2006.01); H01L 27/105 (2023.01);
U.S. Cl.
CPC ...
H01L 27/1104 (2013.01); H01L 21/823412 (2013.01); H01L 21/823807 (2013.01); H01L 21/823821 (2013.01); H01L 21/823878 (2013.01); H01L 21/823892 (2013.01); H01L 27/088 (2013.01); H01L 27/0922 (2013.01); H01L 27/0924 (2013.01); H01L 27/0928 (2013.01); H01L 29/66803 (2013.01); H01L 21/823431 (2013.01); H01L 27/0886 (2013.01); H01L 27/1052 (2013.01); H01L 29/4958 (2013.01); H01L 29/4966 (2013.01); H01L 29/66545 (2013.01);
Abstract

A method for manufacturing a SRAM cell includes forming a first p-well in a semiconductor substrate; forming a first semiconductor fin extending within the first p-well; forming a first mask layer over the first semiconductor fin; patterning the first mask layer to expose a first channel region of the first semiconductor fin, while leaving a second channel region of the first semiconductor fin covered by the first mask layer; with the patterned first mask layer in place, doping the first channel region of the first semiconductor fin with a first dopant; after doping the first channel region of the first semiconductor fin, removing the first mask layer from the second channel region; and forming a first gate structure extending across the first channel region of the first semiconductor fin and a second gate structure extending across the second channel region of the first semiconductor fin.


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