The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 02, 2023

Filed:

Jun. 30, 2021
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Yu-Chang Lin, Hsinchu, TW;

Tien-Shun Chang, New Taipei, TW;

Szu-Ying Chen, Hsinchu, TW;

Chun-Feng Nieh, Hsinchu, TW;

Sen-Hong Syue, Zhubei, TW;

Huicheng Chang, Tainan, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/76 (2006.01); H01L 29/66 (2006.01); H01L 27/092 (2006.01); H01L 29/78 (2006.01); H01L 21/8238 (2006.01); H01L 21/265 (2006.01); H01L 21/324 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66545 (2013.01); H01L 21/265 (2013.01); H01L 21/324 (2013.01); H01L 21/823821 (2013.01); H01L 21/823828 (2013.01); H01L 27/0924 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01);
Abstract

A semiconductor device, and a method of manufacturing, is provided. A dummy gate is formed on a semiconductor substrate. An interlayer dielectric (ILD) is formed over the semiconductor fin. A dopant is implanted into the ILD. The dummy gate is removed and an anneal is performed on the ILD. The implantation and the anneal lead to an enhancement of channel resistance by a reduction in interlayer dielectric thickness and to an enlargement of critical dimensions of a metal gate.


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