The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 18, 2023
Filed:
Jul. 01, 2019
Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;
National Taiwan University, Taipei, TW;
Huang-Siang Lan, Kaohsiung, TW;
CheeWee Liu, Taipei, TW;
Chi-Wen Liu, Hsinchu, TW;
Shih-Hsien Huang, Dongshan Township, TW;
I-Hsieh Wong, Kaohsiung, TW;
Hung-Yu Yeh, Taichung, TW;
Chung-En Tsai, Zhubei, TW;
TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu, TW;
NATIONAL TAIWAN UNIVERSITY, Taipei, TW;
Abstract
A semiconductor device includes a fin extending along a first direction over a substrate, and a gate structure extending in a second direction overlying the fin. The gate structure includes a gate dielectric layer overlying the fin, a gate electrode overlying the gate dielectric layer, and insulating gate sidewalls on opposing lateral surfaces of the gate electrode extending along the second direction. A source/drain region is formed in the fin in a region adjacent the gate electrode structure, and a stressor layer is between the source/drain region and the semiconductor substrate. The stressor layer includes GeSn or SiGeSn containing 10atoms cmor less of a dopant, and a portion of the fin under the gate structure is a channel region.