The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 04, 2023

Filed:

Sep. 08, 2020
Applicant:

Tokyo Electron Limited, Tokyo, JP;

Inventors:

Katie Lutker-Lee, Albany, NY (US);

David O'Meara, Albany, NY (US);

Angelique Raley, Albany, NY (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/027 (2006.01); H01L 21/311 (2006.01); H01L 21/02 (2006.01);
U.S. Cl.
CPC ...
H01L 21/0271 (2013.01); H01L 21/0228 (2013.01); H01L 21/31116 (2013.01);
Abstract

Improved process flows and methods are provided herein for trimming structures formed on a patterned substrate. In the disclosed process flows and methods, a self-aligned multiple patterning (SAMP) process is utilized for patterning structures, such as mandrels, on a substrate. After the structures are patterned, an atomic layer deposition (ALD) process is used to form a spacer layer on the patterned structures. In the SAMP process disclosed herein, a critical dimension (CD) of the patterned structures is trimmed concurrently with, and as a result of, the formation of the spacer layer by controlling various ALD process parameters and conditions. By trimming the patterned structures in situ of the ALD chamber used to form the spacer layer on the patterned structures, the improved process flows and methods described herein provide a CD trim method that does not adversely affect the pattern profile or process throughput.


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