The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 28, 2023

Filed:

Jul. 05, 2019
Applicant:

Kla Corporation, Milpitas, CA (US);

Inventors:

Amnon Manassen, Haifa, IL;

Tzahi Grunzweig, Hillsboro, OR (US);

Einat Peled, Pardes Hanna-Karkur, IL;

Anna Golotsvan, Qiryat Tivon, IL;

Assignee:

KLA CORPORATION, Milpitas, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/67 (2006.01); G06N 10/00 (2022.01); G05B 19/401 (2006.01); G05B 19/4063 (2006.01); G05B 19/418 (2006.01);
U.S. Cl.
CPC ...
H01L 21/67276 (2013.01); G05B 19/401 (2013.01); G05B 19/4063 (2013.01); G05B 19/41875 (2013.01); G06N 10/00 (2019.01); H01L 21/67253 (2013.01); G05B 2219/31281 (2013.01); G05B 2219/32199 (2013.01); G05B 2219/37224 (2013.01);
Abstract

Systems and methods of optimizing wafer transport and metrology measurements in a fab are provided. Methods comprise deriving and updating dynamic sampling plans that provide wafer-specific measurement sites and conditions, deriving optimized wafer measurement paths for metrology measurements of the wafers that correspond to the dynamic sampling plan, managing FOUP (Front Opening Unified Pod) transport through the fab, transporting wafers to measurement tools while providing the dynamic sampling plans and the wafer measurement paths to the respective measurement tools before or as the FOUPs with the respective wafers are transported thereto, and carrying out metrology and/or inspection measurements of the respective wafers by the respective measurement tools according to the derived wafer measurement paths. Quantum computing resources may be used to solve the corresponding specific optimization problems, to reduce the required time, improve the calculated solutions and improve the fab yield and accuracy of the produced wafers.


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