The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 21, 2023
Filed:
Jan. 12, 2018
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Sai Vadlamani, Chandler, AZ (US);
Prithwish Chatterjee, Tempe, AZ (US);
Rahul Jain, Chandler, AZ (US);
Kyu Oh Lee, Chandler, AZ (US);
Sheng C. Li, Gilbert, AZ (US);
Andrew J. Brown, Chandler, AZ (US);
Lauren A. Link, Chandler, AZ (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01F 1/42 (2006.01); H01F 27/38 (2006.01); B32B 27/38 (2006.01); C22C 45/04 (2006.01); H01F 17/00 (2006.01); H01L 23/498 (2006.01); H01F 27/28 (2006.01); H01L 21/56 (2006.01); H01F 17/06 (2006.01);
U.S. Cl.
CPC ...
H01F 1/42 (2013.01); B32B 27/38 (2013.01); C22C 45/04 (2013.01); H01F 17/0033 (2013.01); H01F 27/2804 (2013.01); H01F 27/38 (2013.01); H01L 21/56 (2013.01); H01L 23/498 (2013.01); H01F 17/062 (2013.01);
Abstract
A substrate for an integrated circuit package, the substrate comprising a dielectric, at least one conductor plane within the dielectric, and a planar magnetic structure comprising an organic magnetic laminate embedded within the dielectric, wherein the planar magnetic structure is integrated within the at least one conductor plane.