The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 21, 2023
Filed:
Aug. 18, 2020
Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;
Mill-Jer Wang, Hsinchu, TW;
Ching-Fang Chen, Taichung, TW;
Sandeep Kumar Goel, Dublin, CA (US);
Chung-Sheng Yuan, Hsinchu, TW;
Chao-Yang Yeh, Luzhou, TW;
Chin-Chou Liu, Jhubei, TW;
Yun-Han Lee, Baoshan Township, TW;
Hung-Chih Lin, Hsinchu, TW;
Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;
Abstract
A testing probe structure for wafer level testing semiconductor IC packaged devices under test (DUT). The structure includes a substrate, through substrate vias, a bump array formed on a first surface of the substrate for engaging a probe card, and at least one probing unit on a second surface of the substrate. The probing unit includes a conductive probe pad formed on one surface of the substrate and at least one microbump interconnected to the pad. The pads are electrically coupled to the bump array through the vias. Some embodiments include a plurality of microbumps associated with the pad which are configured to engage a mating array of microbumps on the DUT. In some embodiments, the DUT may be probed by applying test signals from a probe card through the bump and microbump arrays without direct probing of the DUT microbumps.