The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 07, 2023

Filed:

Nov. 25, 2020
Applicant:

Globalfoundries U.s. Inc., Santa Clara, CA (US);

Inventors:

Ephrem G. Gebreselasie, South Burlington, VT (US);

Vibhor Jain, Williston, VT (US);

Yves T. Ngu, Essex Junction, VT (US);

Johnatan A. Kantarovsky, South Burlington, VT (US);

Alain F. Loiseau, Williston, VT (US);

Assignee:

GlobalFoundries U.S. Inc., Santa Clara, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/52 (2006.01); H01L 23/525 (2006.01); H01L 21/8249 (2006.01); H01L 21/02 (2006.01); H01L 27/07 (2006.01); H01L 23/62 (2006.01); H01L 27/115 (2017.01); H01L 27/112 (2006.01); H01L 27/02 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5256 (2013.01); H01L 21/02532 (2013.01); H01L 21/8249 (2013.01); H01L 23/62 (2013.01); H01L 27/0288 (2013.01); H01L 27/0711 (2013.01); H01L 27/115 (2013.01); H01L 27/11206 (2013.01);
Abstract

An electrical fuse (e-fuse) includes a fuse link including a silicided semiconductor layer over a dielectric layer covering a gate conductor. The silicided semiconductor layer is non-planar and extends orthogonally over the gate conductor. A first terminal is electrically coupled to a first end of the fuse link, and a second terminal is electrically coupled to a second end of the fuse link. The fuse link may be formed in the same layer as an intrinsic and/or extrinsic base of a bipolar transistor. The gate conductor may control a current source for programming the e-fuse. The e-fuse reduces the footprint and the required programming energy compared to conventional e-fuses.


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