The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 31, 2023
Filed:
Mar. 15, 2019
Intel Corporation, Santa Clara, CA (US);
Stephen D Snyder, Portland, OR (US);
Leonard Guler, Hillsboro, OR (US);
Richard Schenker, Portland, OR (US);
Michael K Harper, Hillsboro, OR (US);
Sam Sivakumar, Beaverton, OR (US);
Urusa Alaan, Hillsboro, OR (US);
Stephanie A Bojarski, Beaverton, OR (US);
Achala Bhuwalka, Hillsboro, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Techniques are disclosed for non-planar transistors having varying channel widths (Wsi). In some instances, the resulting structure has a fin (or nanowires, nanoribbons, or nanosheets) comprising a first channel region and a second channel region, with a source or drain region between the first channel region and the second channel region. The widths of the respective channel regions are independent of each other, e.g., a first width of the first channel region is different from a second width of the second channel region. The variation in width of a given fin structure may vary in a symmetric fashion or an asymmetric fashion. In an embodiment, a spacer-based forming approach is utilized that allows for abrupt changes in width along a given fin. Sub-resolution fin dimensions are achievable as well.