The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 24, 2023

Filed:

Jun. 04, 2020
Applicant:

Yangtze Memory Technologies Co., Ltd., Wuhan, CN;

Inventors:

Bo Huang, Wuhan, CN;

Lei Xue, Wuhan, CN;

Jiaqian Xue, Wuhan, CN;

Tingting Gao, Wuhan, CN;

Wanbo Geng, Wuhan, CN;

Xiaoxin Liu, Wuhan, CN;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/1157 (2017.01); H01L 27/11524 (2017.01); H01L 27/11539 (2017.01); H01L 27/11551 (2017.01); H01L 27/11578 (2017.01);
U.S. Cl.
CPC ...
H01L 27/1157 (2013.01); H01L 27/11524 (2013.01); H01L 27/11539 (2013.01); H01L 27/11551 (2013.01); H01L 27/11578 (2013.01);
Abstract

A method for forming a memory device includes providing an initial semiconductor structure, including a base substrate; a first sacrificial layer formed on the base substrate; a stack structure, disposed on the first sacrificial layer; a plurality of channels, formed through the stack structure and the first sacrificial layer; and a gate-line trench, formed through the stack structure and exposing the first sacrificial layer. The method also includes forming at least one protective layer on the sidewalls of the gate-line trench; removing the first sacrificial layer to expose a portion of each of the plurality of channels and the surfaces of the base substrate, using the at least one protective layer as an etch mask; and forming an epitaxial layer on the exposed surfaces of the base substrate and the plurality of channels.


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