The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 10, 2023
Filed:
Aug. 03, 2021
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Zhaozhi Li, Chandler, AZ (US);
Sanka Ganesan, Chandler, AZ (US);
Debendra Mallik, Chandler, AZ (US);
Gregory Perry, Santa Clara, CA (US);
Kuan H. Lu, Chandler, AZ (US);
Omkar Karhade, Chandler, AZ (US);
Shawna M. Liff, Gilbert, AZ (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 23/498 (2006.01);
U.S. Cl.
CPC ...
H01L 24/17 (2013.01); H01L 24/09 (2013.01); H01L 24/11 (2013.01); H01L 24/81 (2013.01); H01L 23/49811 (2013.01); H01L 24/06 (2013.01); H01L 24/29 (2013.01); H01L 24/97 (2013.01); H01L 2924/01029 (2013.01); H01L 2924/01047 (2013.01); H01L 2924/01079 (2013.01);
Abstract
An electronic package and method includes a substrate including a plurality of pads on a major surface. An electronic component including a plurality of pads on a major surface facing the major surface of the substrate. A stud bump electrically couples one of the plurality of pads of the substrate to one of the plurality of pads of the electronic component.