The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 03, 2023
Filed:
Jul. 21, 2020
Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;
Hsing-Hsiang Wang, Hsinchu, TW;
Han-Ting Lin, Hsinchu, TW;
Yu-Feng Yin, Hsinchu, TW;
Sin-Yi Yang, Taichung, TW;
Chen-Jung Wang, Hsinchu, TW;
Yin-Hao Wu, Taichung, TW;
Kun-Yi Li, Hsinchu, TW;
Meng-Chieh Wen, Kaohsiung, TW;
Lin-Ting Lin, Taichung, TW;
Jiann-Horng Lin, Hsinchu, TW;
An-Shen Chang, Jubei, TW;
Huan-Just Lin, Hsinchu, TW;
TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu, TW;
Abstract
A method for forming a memory device structure is provided. The method includes providing a substrate, a first dielectric layer, a conductive via, a magnetic tunnel junction cell, a first etch stop layer, and a first spacer layer. The substrate has a first region and a second region, the first dielectric layer is over the substrate, the conductive via passes through the first dielectric layer over the first region. The method includes removing the first etch stop layer, which is not covered by the first spacer layer. The method includes removing the first dielectric layer, which is not covered by the first etch stop layer.