The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 27, 2022

Filed:

Jan. 04, 2019
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Leonard Guler, Hillsboro, OR (US);

Nick Lindert, Portland, OR (US);

Biswajeet Guha, Hillsboro, OR (US);

Swaminathan Sivakumar, Beaverton, OR (US);

Tahir Ghani, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/417 (2006.01); H01L 27/088 (2006.01); H01L 29/06 (2006.01); H01L 21/8234 (2006.01); H01L 29/66 (2006.01); H01L 21/762 (2006.01); H01L 21/02 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7849 (2013.01); H01L 21/02238 (2013.01); H01L 21/76227 (2013.01); H01L 21/823431 (2013.01); H01L 27/0886 (2013.01); H01L 29/0653 (2013.01); H01L 29/41791 (2013.01); H01L 29/6681 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01); H01L 29/7846 (2013.01);
Abstract

Fin trim plug structures for imparting channel stress are described. In an example, an integrated circuit structure includes a fin including silicon, the fin having a top and sidewalls. The fin has a trench separating a first fin portion and a second fin portion. A first gate structure including a gate electrode is over the top of and laterally adjacent to the sidewalls of the first fin portion. A second gate structure including a gate electrode is over the top of and laterally adjacent to the sidewalls of the second fin portion. An isolation structure is in the trench of the fin, the isolation structure between the first gate structure and the second gate structure. The isolation structure includes a first dielectric material laterally surrounding a recessed second dielectric material distinct from the first dielectric material, the recessed second dielectric material laterally surrounding an oxidation catalyst layer.


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