The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 27, 2022

Filed:

Sep. 30, 2016
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Glenn A. Glass, Portland, OR (US);

Anand S. Murthy, Portland, OR (US);

Nabil G. Mistkawi, North Keizer, OR (US);

Karthik Jambunathan, Hillsboro, OR (US);

Tahir Ghani, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/06 (2006.01); H01L 29/78 (2006.01); H01L 29/08 (2006.01); H01L 29/66 (2006.01); H01L 29/423 (2006.01); H01L 29/786 (2006.01); B82Y 10/00 (2011.01); H01L 29/775 (2006.01); H01L 21/02 (2006.01); H01L 21/8234 (2006.01); H01L 29/10 (2006.01); H01L 29/165 (2006.01);
U.S. Cl.
CPC ...
H01L 29/0673 (2013.01); B82Y 10/00 (2013.01); H01L 21/02527 (2013.01); H01L 21/02532 (2013.01); H01L 21/823412 (2013.01); H01L 21/823431 (2013.01); H01L 21/823437 (2013.01); H01L 29/0847 (2013.01); H01L 29/1033 (2013.01); H01L 29/165 (2013.01); H01L 29/42392 (2013.01); H01L 29/66 (2013.01); H01L 29/6681 (2013.01); H01L 29/66439 (2013.01); H01L 29/66545 (2013.01); H01L 29/775 (2013.01); H01L 29/785 (2013.01); H01L 29/78696 (2013.01);
Abstract

Techniques are disclosed for forming nanowire transistors employing carbon-based layers. Carbon is added to the sacrificial layers and/or non-sacrificial layers of a multilayer stack forming one or more nanowires in the transistor channel region. Such carbon-based layers reduce or prevent diffusion and intermixing of the sacrificial and non-sacrificial portions of the multilayer stack. The reduction of diffusion/intermixing can allow for the originally formed layers to effectively maintain their original thicknesses, thereby enabling the formation of relatively more nanowires for a given channel region height because of the more accurate processing scheme. The techniques can be used to benefit group IV semiconductor material nanowire devices (e.g., devices including Si, Ge, and/or SiGe) and can also assist with the selective etch processing used to form the nanowires. The carbon concentration of the sacrificial and/or non-sacrificial layers can be adjusted to facilitate etch process to liberate nanowires in the channel region.


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